Both LoRa® and Sigfox technologies are designed to operate under a Low Power Wide Area Network (LPWAN) protocol. This protocol was created to wirelessly connect battery operated ‘things’ to the internet in regional, national or global networks with requirements such as bi-directional communication, end-to-end security, mobility and localization services [2]. LoRa® and Sigfox are IoT oriented, where low power and low bit rate are common characteristics. Both technologies use ISM (Industrial, Scientific and Medical) radio band, a license-free sub-gigahertz radio frequency band, which uses 868 MHz in Europe and 902 MHz in the Americas [3].
LoRa® is the physical proprietary radio modulation technique. It’s based on spread-spectrum modulation techniques derived from chirp spread spectrum (CSS) technology, a patented technology by Semtech Corporation [4]. LoRaWAN (Long Range Wide-Area Network) protocol is supported by the LoRa Alliance association since 2015.
Sigfox employs the Differential Binary Phase-Shift Keying (DBPSK) for uplink and the Gaussian Frequency Shift Keying (GFSK) for downlink that enables communication. It utilizes a wide-reaching signal that passes freely through solid objects, called “Ultra Narrowband” and requires little energy. The network is based on one-hop star topology and requires a mobile operator to carry the generated traffic. The signal can also be used to easily cover large areas and to reach underground objects. Sigfox network is supported by a French global network operator founded in 2010 [3].
System-in-Package Design
The design was developed based on the System-in-Package (SiP) technology, which is a circuit whose passive components and chips, or dies, are all mounted on the same substrate, and are enclosed in a chip carrier package, thus configuring a single component.
In this SiP design, the connection of the die that integrates the microcontroller and transceiver, and the rest of the circuit components is done using golden wires, which are bonded to the substrate surface.
The package type chosen for this SiP design is a Land Grid Array (LGA) package.
The whole boundary of this LGA package is fulfilled with 2 columns of 20 pins and 2 rows of 12 pins, totalizing 64 pins that outline the LGA package.
Inside the LGA package are 6 power pins, which are much larger than the 64 pins on the boundary, and they are matched in pairs for VDD and GND connections.
Almost all of the 64 pins on the boundary of the LGA package are connected to the die pads of the microcontroller die, thus allowing the access of the signals of this component to the Printed Circuit Board (PCB) where the SiP device is mounted on
The SiP design flow is shown in Fig. 1:
A. System Level Design
This project combines an MCU, a sub-gigahertz radio frequency transceiver, a 3-axis accelerometer and an RF Matching Circuit into a single package to operate both in LoRa® and Sigfox networks.
The microcontroller with a sub-GHz radio incorporated altogether was selected, because it was taken into consideration the digital interfaces, the final cost and its current consumption when in deep sleep mode, RF output power up to +22dBm, wide power supply range supported, memory size, and firmware support.
It was also considered that the sub-GHz radio frequency transceiver incorporated into the microcontroller die is capable to operate both in LoRa® and Sigfox networks.
In this project, the RF matching circuit was incorporated into the SiP design to speed up the customer’s final product in order to avoid RF simulations and adjustments. This way, only few components are needed for its operation.
B. SiP Layout Design
The layout of the SiP device was done using Allegro Package Designer+ (APD+) development tool, with the SiP Layout option, from Cadence® manufacturer.
The circuit of the SiP Design totalizes 21 devices assembled, using the following devices:
- one microcontroller die;
- one 3-axis accelerometer;
- one wide band RF switch for signal selection;
- 18 discrete passive SMT components.
The stackup of the substrate is composed of 2 copper layers (TOP and BOTTOM), and a copper clad laminate core, in a total thickness of 100um.
The layout design is divided into 3 portions: RF circuit; microcontroller die; and 3-axis accelerometer.
The RF circuit has its own routing, with some rules that make it distinct from all the rest of the routing in the design.
The design challenge was to keep the performance of the transceiver, integrating the most part of the RF components in the SiP Package, and through design exploration using Electromagnetic simulation, we defined the best layout and routing for the RF portion so that the maximum performance of the transceiver could be reached.
In the routing of RF circuit, there is an RF reference, closely located to the traces, avoiding any loss.
The same way, a few from a bunch of the binary communication signal traces were routed closely to their reference.
Special care was taken with some signal traces that were routed inside the ground copper areas in such way that the plowing and self-healing dynamic features of these areas guaranteed the complete shielding all along the traces, in order to avoid stretches with different impedances and also cross-talk / EMI issues. The layout views can be seen in Fig. 2:
C. Performance Simulation
The simulation of the SiP device was done using Electronics Desktop environment, with the HFSS 3D Layout Electromagnetic simulation tool option, from ANSYS® manufacturer.
Some different analysis were performed, such as transient signals, S-Parameters (gain and insertion / return loss) and 3D polar Electromagnetic field, during the layout design process, in order to find the most adequate layout parameters that gave the best simulation results.
Ports were placed between the input and the output of the RF circuit, and a transient stimulus was applied on the input and a response was analyzed in the output.
In Fig. 3, there are some plots of the simulations executed in SiP device during the design:
Results
The achievement of the SiP design driven for manufacturing required the development team lots of interactions with the manufacturer group, besides the study and evaluation made of several substrate layout specifications in the beginning stages of the design, due to specially the small dimensions of the device.
Once the device was ready for the manufacture, all of its features worked perfectly fine, and the validations of all of its manufacturing processes and specifications, from package assembly to performance measurements were able to flow without any problem.
A.Package Assembly
The SiP packaging assembly was processed using the substrate arranged in a matrix that contains 140 units in one panel.
The process used during the prototype assembly is described as follows:
(i) SMT Process (Screen Printer, Pick & Place and Reflow) for passive components, accelerometer, microcontroller and RF switch;
(ii) Wafer Preparation (Grinding, Frame Ring Mounter, and Dicer) to prepare and dicing the wafer (in individual dice);
(iii) Wire Bonder to attach the die (using a specific tape) on the substrate;
(iv) Wire Bonder for internal connection of die with substrate using golden wires;
(v) Compression Mold for encapsulation using Epoxy Mold Compound;
(vi) And finally, the strip is singularized to have the final device.
Figure 4 below shows with more details the process used in the Package Assembly:
In addition, the device was submitted in an internal qualification process to evaluate the reliability and functional performance.
In Fig. 5, there are some process stages, used during the Package Assembly:
B. Performance and Measurements Evaluation
The SiP’s performance was evaluated using a power supply, a digital multimeter and spectrum analyzer. The device was mounted on a breakout board that provides a serial interface to exchange data with the device under test (DUT) through AT commands, and it connects the measurement to the instruments.
Fig. 6: below illustrates the output power of the device when transmitting LoRa® modulation at 915.2 MHz, specified to 125 kHz bandwidth and spread factor of 7.
Table 1 below presents further current and output power measurements for different LoRa® configuration.
| LoRa Configuration | Measurements | ||
|---|---|---|---|
| SF | BW(kHz) | Current (mA) | Tx Power (dBm) |
| 12 | 125 | 116.04 | 21.026 |
| 11 | 125 | 118.08 | 21.049 |
| 10 | 125 | 115.449 | 20.99 |
| 9 | 125 | 120.72 | 21.021 |
| 8 | 125 | 112.59 | 21.026 |
| 7 | 125 | 113.48 | 21.027 |
| 8 | 500 | 115.99 | 21.05 |
The following Fig. and Table 2 shows the results of the phase noise measurement obtained when transmitting a Continuous Wave:
| Traces | Frequency Offset (kHz) | Phase Noise (dBc/Hz) |
| 1 | 25.0 | -96.20 |
| 2 | 50.0 | -97.03 |
| 3 | 100.0 | -98.81 |
| 4 | 300.0 | -106.98 |
| 5 | 1000.0 | -119.85 |
The device presented a current consumption of 10 mA when in receiving mode and 10uA in sleep mode.
Conclusions
The development of the System-in-Package (SiP) Substrate Design that contains the features of microcontroller unit, sub-gigahertz radio-frequency transceiver, 3-axis accelerometer and RF matching circuit, all of them integrated in the same package, involves different areas and expertise, from the front-end Design Engineer to the Assembly Process Engineer.
The design meets all RF requirements necessary to be used in Sigfox and LoRa® communication protocols, and all these features already mentioned in the study were achieved in a small device with 7.5 mm x 11 mm x 1.2 mm package size.
references: [1] M. Bloechl, “SigFox Vs. LoRa: A Comparison Between Technologies & Business Models”. Accessed on: April 06, 2022. [Online]. Available: https://www.link-labs.com/blog/sigfox-vs-lora
[2] LoRa® Alliance, “What is LoRaWAN® Specification”. Accessed on: May 02, 2022. [Online].
Available: https://lora-alliance.org/about-lorawan/
[3] Daviteq, Marketing Department, “SigFox Technology – Make Things Come Alive”. Accessed on: May 02, 2022. [Online]. Available: https://www.daviteq.com/blog/en/sigfox-technology-make-things-come-alive/
[4] Semtech, “What Is LoRa®?”. Accessed on: May 02, 2022. [Online]. Available: https://www.semtech.com/lora/what-is-lora
[5] G. Dimayuga, R. Agustin, J. Talledo, “Elimination of delamination and solder flow-out in a new System In Package (SIP) with large surface mount device (SMD)”. 23rd ASEMEP National Technical Symposium.
